1. Field
This disclosure relates generally to semiconductor devices, and more specifically, to reducing power consumption in semiconductor devices.
2. Related Art
Semiconductor integrated circuit chips (ICs) generally include a semiconductor substrate supporting various types of circuits such as random access memory (RAM), arithmetic logic units (ALUs), multiplexers (MUXs), and addressable registers, interconnected by various data signal paths. These circuits are typically formed of various lower level logic circuits, or “cells,” such as NAND gates, NOR gates, inverter gates, and various types of latches and flip-flops. The cells are typically interconnected such that the output of each connects, through respective signal paths, to inputs of other cells. Currently available large scale ICs can include millions of these cells, with each cell containing PMOS and NMOS transistors.
To save time during the design process, circuit representations of the lower level logic circuits can be included in libraries of standard cells that are accessible to circuit designers using interactive design workstations. The more complex circuits are designed using the standard cells as building blocks.
NMOS transistors are built using a well doped with P-type material in a substrate, and PMOS transistors are built using a well doped with N-type material in the substrate. Well proximity effects refer to NMOS or PMOS transistors located close to an edge of a respective well exhibiting different threshold voltage and drive current than devices located farther from the edge of the well. An integrated circuit composed of one or more various types of logic circuits requires a finite amount of time for a signal to propagate from the input to the output of the circuit. Circuits composed of NMOS and PMOS transistors with a low threshold voltage exhibit fast response but have correspondingly high leakage. To reduce power consumption due to leakage current, the threshold voltage can be raised, with an attendant decrease in the operating speed of the device.
The circuits typically have a fixed amount of time to operate to meet timing requirements. At low clock rates, there is typically no difficulty in arranging the circuits to ensure that timing requirements are met. Meeting the timing requirements becomes more challenging, though, as clock frequencies become higher. Additionally, as the number of devices in integrated circuits increases, it is desirable to conserve power wherever possible. Thus, the higher speed and attendant higher leakage current to meet timing requirements conflicts with efforts to conserve power.